The present invention relates to a semiconductor device, a diagnostic test, and a diagnostic test circuit in a semiconductor device. For example, the present invention can be suitably used for a diagnosis of a plurality of CPU cores.
To achieve high calculation performance, a CPU (Central Processing Unit) system having a multi-core architecture is desirable. However, if a failure occurs in one of the CPU cores, it is necessary to immediately detect the failure and bring the system into a safe state in view of functional safety. However, the use of a program (software) for performing a self-diagnosis based on an instruction set to perform a fault diagnosis of a high-performance CPU cannot provide a satisfactory result in terms of both the fault detection rate (diagnosis coverage) and the diagnosis time (program execution time). For example, even if a self-diagnosis program by which high diagnosis coverage can be achieved can be created, it is certain that the execution time of that self-diagnosis program will be considerably long. Therefore, the execution of that program in a normal operation state lowers the operation performance, thus making it unrealistic.
Japanese Unexamined Patent Application Publication No. H10-11319 discloses a technique in which a boundary scan test for a plurality of CPU boards is carried out by using one scan chain extending through the plurality of CPU boards and a fault diagnosis of the plurality of CPU boards is thereby performed. Further, Japanese Unexamined Patent Application Publication No. 2012-194111 discloses a technique in which when the execution of an application is requested while a fault diagnosis of a process is being performed by performing a scan test, the scan test is interrupted and the application is executed.